A variety of memory devices are in common use in a wide range of electronic devices. A common variety of memory devices are dynamic random access memory (“DRAM”) devices, which are used in a variety of applications, such as for system memory in computer systems. As is well known in the art, a DRAM device includes a large number of DRAM memory cells that are essentially individual capacitors that store one of two voltage levels corresponding to respective binary values of a data bit. As also well known in the art, capacitors, including those used as DRAM memory cells, leak charge and therefore cannot retain a voltage level indefinitely. For this reason, it is necessary to periodically restore the voltage initially stored in a DRAM memory cell capacitor, which is accomplished using a process known as “refresh.”
Typical DRAM memory cells and associated circuitry are shown in FIG. 1. The DRAM memory cells 14 (only eight are shown in FIG. 1) each include two capacitor plates 16, 18. One of the plates 16 is known as a cell plate that is generally common to all of the memory cells 14 in at least a bank of memory cells. The cell plate 16 in usually maintained at a voltage that is equal to one-half the supply voltage VCC. The other plate 18 of each memory cell 14 is coupled to either a digit line D or a complementary digit line D# by respective access transistors 20. The gates of the access transistors 20 for all of the memory cells 14 in each row are normally connected to each other and to a common word line W. The access transistors 20 for all of the memory cells 14 in each column are connected to a common pair of digit lines D, D#. The digit lines D, D# for each column are coupled to a respective sense amplifier 30 and to a respective equilibration circuit 34.
In operation, the equilibration circuit 34 for each column couples the digit lines D, D# for the respective column to each other, and it also couples the digit lines D, D# for the respective column to VCC/2. Thus, after the digit lines D, D# have been equilibrated, the voltage on both of the digit lines D, D# is one half the supply voltage.
When a memory cells 14 in a row are to be read, an actuation signal is applied to the word line W for that row, thereby causing all of the access transistors 20 in the row to couple a respective memory cell 14 in the row to one of a respective pair of digit lines D, D#. The voltage of the digit line D or D# to which a memory cell 14 has been coupled will then change slightly depending on which voltage is stored by the memory cell 14. If the memory cell is storing zero volts, the voltage of the digit line D or D# will decrease slightly. If the memory cell is storing VCC, the voltage of the digit line D or D# will increase slightly. The reason why the change in voltage is only slight is that the digit lines D, D# have substantial intrinsic capacitance. The voltage on the digit lines D, D# increases or decreases by charge sharing, and, since the capacitance of the digit line D, D4 is substantially greater than the capacitance of the memory cell 14 to which the digit line D or D# is coupled, the change in voltage is only slight. However, the voltage on one digit line D or D# will nevertheless be greater than or less than the voltage on the other digit line D# or D, respectively. In practice, the voltage stored by the memory cell 14 will not always be either VCC or ground because of the leakage of charge to or from the memory cell 14. However, a voltage stored by the memory cell 14 that is greater than VCC/2 will still increase the voltage on the digit line D or D# to which it is coupled so that the voltage on the digit line D or D# will be greater than the voltage on the other digit line D# or D, respectively. Similarly, a voltage stored by the memory cell 14 that is less than VCC/2 will still decrease the voltage on the digit line D or D# to which it is coupled so that the voltage on the digit line D or D# will be less than the voltage on the other digit line D# or D, respectively.
The sense amplifier 30 for each pair of digit lines D, D# senses which digit line has the greater voltage and which has the lesser voltage, and then drives the digit lines D, D# to either ground or VCC. The sense amplifier 30 will drive the digit line D or D# having the greater voltage to VCC, and it will drive the digit line D or D# having the lesser voltage to ground. The data bit stored in each column can then be read by coupling the digit lines for each column to respective differential amplifiers (not shown).
When the sense amplifier 30 drives one of the digit lines D or D# to VCC and the other digit line D# or D, respectively, to ground, the memory cell for the respective column is still coupled to the digit line D or D# by the access transistor 20. As a result, the full voltage (VCC or ground) to which the digit line D or D# is driven is coupled to the memory cell 14 for each column. Reading the memory cells 14 in a row thus restores the memory cells 14 to the full voltage to which they had previously been charged. For this reason, the above process is performed periodically for the memory cells 14 in each row by a process known as refresh, although the data “read” in each column is not coupled to the differential amplifier.
After the memory cells 14 have been read or refreshed, the actuating signal coupled to the word line W for the actuated row terminates, thereby substantially isolating the memory cells 14 from the respective digit line D or D# to which they were coupled. The equilibration circuit 34 for each column then drives the digit lines D, D# in the respective column to VCC/2, as explained above, in preparation for a subsequent read or refresh of the same or a different row of memory cells 14.
The refresh process described above can cause a DRAM device to draw a substantial amount of current. Although the current drawn by each column is not significant, conventional DRAM device include a large number of columns, i.e, on the order of 10,000 or more. Therefore, even though the current drawn by each column of memory cells 14 may not be significant, the current drawn by all of the columns in a DRAM device being refreshed can be very significant. Even more significant are situations in which a large number of DRAM devices in a system are simultaneously refreshed. When a large number of DRAM device are simultaneously refreshed, the current drawn by all of the DRAM devices being refreshed can exceed the current supplying capabilities of a system containing the DRAM devices or at least create voltage transients or “spikes” on supply voltage lines that can cause other circuits that are connected to the same supply voltage lines to malfunction.
The memory cells 14 are refreshed using several different types of refresh procedures. In an auto-refresh procedure, and with some complex system designs, refreshes to all of the DRAM devices in a system may be initiated independently of each other. Therefore, refreshes can occur in the DRAM devices at different times so that the refresh current can be averaged over a period of time, thus limiting the peak current drawn. As a result, the problem of excessive peak current may not a problem for auto-refresh operations.
Excessively large peak current draws are normally not a problem for memory read operations because generally only a single DRAM device or single rank responds to each read command. Therefore, although the peak current drawn by the DRAM device being read may be substantial, it is the only DRAM device or rank in the system that is drawing such current.
Excessively large peak current draws may be a problem for self-refresh operations. In a self-refresh operation, a device such as a memory controller (not shown) may issue an self-refresh command to all of the DRAM devices or multiple ranks in a system. All of the DRAM devices then respond to the self-refresh command by immediately initiating a refresh of all of the memory cells 14 in the respective DRAM devices or multiple ranks. It is in this situation that the peak current drawn by the DRAM devices can cause the type of problems described above.
The problem of excessive currents resulting from DRAM refreshes has been recognized, and various attempts have been made to solve or at least alleviate this problem. In one conventional approach, a DRAM device includes internal refresh circuitry that staggers the refresh of each of several banks of memory cells so that all of the memory cells in the DRAM device are not being refreshed at the same time. Although this technique does minimize the current drawn by each DRAM device, it does not entirely solve the problem of a large number of DRAM devices in a system simultaneously responding to a self-refresh command. For example, when an self-refresh command is issued, all of the DRAM devices in the system will immediately initiate a refresh, albeit the refresh will occur simultaneously in only one memory bank of each DRAM device rather than in all of the memory banks of all of the DRAM devices. However, in systems with a large number of DRAM devices, the problem of excessive current draw can nevertheless be significant.
There is therefore a need for a technique that prevents all of the DRAM devices in a system from simultaneously initiating a refresh operation, such as in response to a self-refresh command issued to all of the DRAM devices in the system.